This invention relates to a receiver which is intermittently operable and, more particularly, to a technique which can make a code division multiple access (CDMA) receiver intermittently carry out reception operation.
Recently, development of a mobile communication system is remarkable and there have been strong demands in the fields of mobile communication terminals for use in the mobile communication system. In general, each of the mobile communication terminals of the type described in driven by a battery which has a finite lifetime. Accordingly, in order to extend a use time in the mobile communication terminal without replacement of the battery frequently, it is necessary to remove consumption of useless current in the mobile communication terminals as much as possible. As such technique, in a case where the mobile communication terminal is put into a wait state, a method of making the mobile communication terminal operate intermittently is adapted.
In a case where this intermittent operation is realized in a spread spectrum technique such as the code division multiple access (CDMA), attentions will be made as regards points which will presently be described.
In general, it is known as characteristics in the receiver for receiving a spread spectrum received signal such as a CDMA receiver that reception information itself cannot be decoded if a synchronous state between the spread spectrum received signal and a despreading code for use in despreading is strictly matched. In addition, for this purpose, a clock signal used as a reference signal of synchronous timings preferably has a high frequency and is stable.
Those situations are required not during reception but also in a case of making the receiver establish the synchronous state operate intermittently. That is, it is necessary to ensure a correct synchronization between the spread spectrum received signal and the despreading code as rapidly as possible on making the receiver operate intermittently transit from a reception operation stop state to a reception operation state.
Under the circumstances, that is, in consideration of a balance of the above-mentioned low consumption of current and necessity of a rapid synchronous acquisition on transiting from the reception operation stop state to the reception operation state, various conventional methods are already proposed as methods for making the receivers such as the CDMA receivers operate intermittently. The conventional methods are classified into first and second conventional methods as follows.
The first conventional method comprises the step of making only a high-frequency oscillation section operate when operations of other receiving parts stop during the reception operation stop state in an intermittent operation state, thereby holding a synchronous established state. The high-frequency oscillation section comprises a high-frequency oscillator acting as a time reference oscillator for high precision and a high-speed counter for frequency dividing a high frequency signal outputted from the high-frequency oscillator to produce a divide signal. That is, in the first conventional method, the receiver is put into, during the intermittent operation state, a hot standby state where the high-frequency oscillation section operates while the operations of the other receiving parts stop for a reception operation stop time interval of the reception operation stop state.
The second conventional method comprises the step of resetting a phase state of the despreading code whenever the receiver is put into the reception operation state in the intermittent operation state to resynchronize the despreading code to the spread spectrum received signal in accordance with an initial synchronous acquisition procedure. In other words, in the second conventional method, the receiver is put into, during the intermittent operation state, a sleep state where operation of the high-frequency oscillation section stop for the reception operation stop time interval.
Various CDMA receivers of the type are already known. By way of example, Japanese Unexamined Patent Publication of Tokkai No. Hei 5-191,375 or JP-A 5-191375 discloses a spread spectrum system receiving equipment which is capable of execute a synchronous acquisition of a spreading code in a short time at the time of dormant state in an intermittent receiving operation and which is capable of reducing the power consumption. According to JP-A 5-191375, in the case of switching to a dormant state from reception at the time of intermittent receiving operation, a switch is connected to a fixed frequency oscillating circuit, and by driving a local spreading code generating circuit by its free-running clock, a phase difference of a spreading code is prevented from becoming large, the switch is connected to a phase delaying circuit, a phase of a local spreading code generated by the code generating circuit is delayed by a portion of a phase shift of the local spreading code estimated at the time of dormant state, and subsequently, the switch is connected to a phase advancing circuit, so that a phase of an output of the code generating circuit advances little by little, and at the moment a large correlation value is generated in an output of a correlator in such a state, the switch is connected a delay lock loop, and switched to a regular synchronization tracking operation.
Japanese Unexamined Patent Publication of Tokkai No. Hei 7-123,024 or JP-A 7-123024 discloses a method for initial pull-in of automatic frequency control and its receiver in which a time required when initial pull-in of automatic frequency control is made available in a spread spectrum communication. According to JP-A 7-123014, an AFC circuit is composed of a mixer, an A/D converter, a digital matched filter (DMF), an oscillator (OSC), a frequency discriminator, a D/A converter, an AFC control circuit, and a voltage controlled oscillator (VCO). Then, a sample clock frequency outputted from the oscillator is selected to be a frequency higher than or lower than one-chip frequency of a chip clock frequency of a sender side included in a received IF input by about two cycles. Thus, fluctuation in the correlation due to frequency deviation between transmission and reception clock signals is suppressed in a short time and the clock generated from the voltage controlled oscillator is synchronized quickly with the chip clock frequency.
Japanese Unexamined Patent Publication of Tokkai No. Hei 8-321,804 or JP-A 8-321804 discloses a communication terminal equipment.which is capable of considerable reducing power consumption at the time of intermittent reception in the communication terminal equipment. According to JP-A 8-321804, the state value of a second spreading code generation means at the time of next starting is set in a register means and a timer means is operated. Second and first spreading code generation means and a reception system circuit are stopped and a system becomes a sleep state. At the time or restarting by the time-out of the timer means, the reception system circuit is operated and the second spreading code generating means is operated from the state value which is set in the register means. Furthermore, an intermittent reception means operating the first spreading code generation means from an initial state is provided. Thus, the first and second spreading code generation means can be stopped at the time of non-reception, and power consumption at the time of intermittent reception can considerably be reduced.
Japanese Unexamined Patent Publication of Tokkai No. Hei 9-284,151 or JP-A 9-284151 discloses a receiver, a reception method, and a communication system which are capable of keeping the synchronization precision in the standby state and of caving the power consumption. According to JP-A 9-284151, a control circuit applies power supply control or the like to each circuit such as a synchronization correction signal generating circuit, a pseudo-noise (PN) code generator and an information decoding circuit in each independent timing. The control circuit controls driving the information decoding circuit once for N times of driving each circuit such as the synchronization correction signal generating circuit synchronously with the timing of driving each circuit such as the synchronization correction signal generating circuit.
Japanese Unexamined Patent Publication of Tokkai No. Hei 9-321,667 or JP-A 9-321667 discloses a receiver for a CDMA (code division multiple access) system which is capable of reducing the power consumption in the standby state thereof. According to JP-A 9-321667, a received spread spectrum signal is demodulated into base band signals at multipliers and the demodulated signals are given to a complex matched filter. The complex matched filter is driven intermittently by a power supply control section to attain synchronization acquisition of a reception signal. When a power calculation section detects that an output of the complex matched filter has a peak output of a prescribed value or over, a correlation device control section operates n-sets of correlation devices and synchronization of the reception signal is traced and despread is conducted, outputs of the correlation devices are subjected to RAKE synthesis at a RAKE synthesis and demodulation section and demodulated.
Although the above-mentioned Japanese Unexamined Patent Publications are different from one another in detail, those Publications are roughly divided into the above-mentioned first and second conventional methods.
As described above, on making the conventional CDMA receiver operate intermittently, the correct synchronization between the spread spectrum received signal and the despreading code is ensured whenever a reception operation is started by adopting either the first conventional method or the second conventional method.
However, all of the above-mentioned first and second conventional methods have peculiar problems in the manner which will presently be described, each of the above-mentioned first and second conventional methods is difficult to realize the intermittent operation which can scheme true low consumption of current.
The first conventional method makes the components except for the high-frequency oscillation section operate intermittently as described above and it is therefore impossible to stop operation of the high frequency oscillation section. In general, as being understood from the lifetime of the battery in such a clock or watch, a low-frequency oscillator and a low-speed counter arc operable in extremely small current while the high-frequency oscillator and the high-speed counter consume relatively large current. However, in spite of necessary of the relatively large current, the first conventional method cannot stop the operation of the high-frequency oscillator and the high-speed counter and it results in decreasing a degradation effect of the consumed current due to the intermittent operation. In addition, as described above, inasmuch as precision in a measured time interval is good when a reference oscillator has a high oscillator frequency and is stable in a case where a time measurement is carried out in the receiver by using a free-running oscillator, it is impossible to simply replace a combination of the high-frequency oscillator and the high-speed counter with a combination of the low-frequency oscillator and the low-speed counter.
On the other hand, it is difficult in the second conventional method to carry out a rapid synchronous acquisition without increase in the consumed current in a case where the state is transited from the stop state to the operating state. Specifically, if the second conventional method is adopted with the low consumption of current maintained, the conventional method takes longer to resynchronize. As a result, the receiver must start resynchronization operation after a lapse of a short time interval from a time when the receiving operation stops and the receiver may have a substantially short time interval for which the receiver can stop the receiving operation. Under the circumstances, the degradation effect of the consumed current due to the intermittent operation lowers. In addition, the second conventional method is disadvantageous in that it is impossible to carry out the intermittent operation itself in extreme case.
It is therefore an object of this invention to provide a receiver and an intermittent receiving method, which are capable of really reaching low consumption of current.
Other objects of this invention will become clear as the description proceeds.
On describing the gist of an aspect of this invention, it is possible to be understood that a code division multiple access (CDMA) receiver intermittently receives a spread spectrum received signal using a despreading code having a chip duration. The CDMA receiver is alternately put into a reception operation state and a reception operation stop state for an intermittent reception state. The reception operation stop state continues for a reception operation stop time interval between a reception stop starting time instant and a reception return time instant.
According to the aspect of this invention, the above-understood CDMA receiver comprises a high-resolution time reference generating section for generating a high-resolution timing signal having a high-resolution period which is shorter than the chip duration and a low-resolution time reference generating section for generating a low-resolution timing signal having a low-resolution period which is longer than the high-resolution period. Connected to the high-resolution time reference generating section, a state control section puts, for substantially the operation stop time interval, the CDMA receiver into a cold standby state where the high-resolution time reference generating section does not operate while the low-resolution time reference generating section operates. On or immediately before the reception return time instant, the state control section puts the CDMA receiver into a hot standby state where the high-resolution time reference generating section operates.
On describing the gist of an aspect of this invention, it is possible to be understood that a method is of intermittently receiving a spread spectrum received signal using a despreading code having a chip duration in a code division multiple access (CDMA) receiver which is alternately put into a reception operation state and a reception operation stop state for an intermittent reception state. The reception operation stop state continues for a reception operation stop time interval between a reception stop starting time instant and a reception return time instant. The CDMA receiver comprises a high-resolution time reference generating section for generating a high-resolution timing signal having a high-resolution period which is shorter than the chip duration and a low-resolution time reference generating section for generating a low-resolution timing signal having a low-resolution period which is longer than the high-resolution period.
According to this invention, the afore-mentioned method comprises the steps of putting, for substantially the operation stop time interval, the CDMA receiver into a cold standby state where the high-resolution time reference generating section does not operate while the low-resolution time reference generating section operates and of putting, on or immediately before the reception return time instant, the CDMA receiver into a hot standby state where the high-resolution time reference generating section operates.